Semiconductor devices, such as complementary-metal-oxide semiconductor (CMOS) devices, complementary bipolar CMOS (BiCMOS) devices, bipolar junction transistors (BJTs) and field effect transistors (FETs), and microelectromechanical systems (MEMS) devices, that are fabricated on a front side of a semiconductor wafer, usually require conductive structures, such as through substrate vias (TSVs), to provide electrical connection to a back side of the semiconductor wafer. The connection to the TSVs from the back side of the semiconductor wafer can be made by grinding the back side using wafer thinning, polish or grinding equipment with an intention of grinding into the TSVs.
According to a conventional wafer thinning approach, a semiconductor wafer is temporarily bonded to a handle wafer using bonding material, such as polymeric material, which requires low temperature processing, for example, under 250-300° C. The semiconductor wafer is ground using standard grinding equipment, which grinds the entire diameter of the semiconductor wafer, thereby reducing the overall thickness across the semiconductor wafer. After the grinding action, a polish action, such as Chemical Mechanical Polishing (CMP), wet etch or plasma etch, is required to polish and remove residues from the back side surface. In the conventional approach, the thinned semiconductor wafer needs to be debonded from the handle wafer. The bonding material tends to outgas at 200-300° C., thereby limiting high temperature wafer processing. Also, grinding into metallic filler material in the vias within the semiconductor wafer can lead to destruction of the grinding wheel and cause subsurface damage or even destruction of the semiconductor wafer. In addition, the final polish action, such as CMP, wet etch or plasma etch, can cause further stress to the thinned semiconductor wafer, which can lead to cracking of the semiconductor wafer rendering dies on the semiconductor wafer unsuitable for further processing. As a result, reducing the depth of the TSVs in thin semiconductor wafers presents difficulties. The conventional wafer thinning approach cannot produce shallow TSVs of 300 μm or less.
As semiconductor dies used in electronic products continue to shrink in size, there is a need in the art for high volume manufacturing of thinned processed semiconductor wafers having devices and TSVs, for example, in 150 μm or less thickness range, without causing cracking or subsurface damage to the semiconductor wafers.